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NXP Semiconductors /LPC800 /PIN_INT /CIENF

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Interpret as CIENF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CENAF0RESERVED

Description

Pin interrupt active level (falling edge) interrupt clear register

Fields

CENAF

Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data